1. Field of the Invention
The present invention is related generally to component testing and, in particular to testing input levels on integrated circuits.
2. Background Information
When products are sold to original equipment manufacturers (OEMs) the products are usually accompanied by device specifications. The specifications typically include acceptable operating conditions, connection recommendations, direct current (DC) specifications, and alternating current (AC) specifications. The device is commonly warranted to perform according to the specifications.
Product manufacturers perform certain tests on the devices in order to guarantee the product complies with the specifications. For example, when the DC specifications state that the “input low voltage” (VIL) is three hundred millivolts at a minimum and eight hundred millivolts at a maximum, the manufacturer has tested the product to ensure that a DC voltage between three hundred millivolts and eight hundred millivolts applied to the part is interpreted as a logical “zero.” Similarly, when the DC specifications state that the “input high voltage” (VIH) is two volts at a minimum and the supply voltage (VCC) at a maximum, the manufacturer has tested the part to ensure that a DC voltage between two volts and Vcc applied to the part is interpreted as a logical “one.”
Test paradigms are defined generally by the kind of test (functional or structural), and the kind of tester that delivers and stores the test (functional or structural) In general, structural testers have fewer direct connections to the device under test than functional testers, and depend on many DFT (Design For Testability) features designed into the device to perform equivalent tests to the functional testers. Because the design and silicon area costs are much lower than the tester costs, it may be advantageous for any product to utilize structural testers and DFT hooks to support them whenever possible.
Functional tests target device functionality and attempt to ensure that the device is functioning correctly. Functional tests are primarily performed for architectural verification and silicon debug, but can be used for manufacturing testing as well. A ITS9000 series tester from Schlumberger is an example of a well-known functional tester. An advantage of functional testers is that they commonly drive a large number of input/output (I/O) pins at high clock rates with great timing accuracy. When testing integrated circuits, for example, a functional tester allocates a tester channel to each pin of the device under test. Typically, in levels testing an input signal value is applied to the input pins of the part. The input signal value swings up and down between a logical “one” and a logical “zero,” respectively, beyond an offset amount from a reference voltage. The product input circuitry (e.g., sense amplifier) trips in one direction for a logical “one” and in the other direction for a logical “zero.”
Testing products, especially in high volumes typical of manufacturing environments using functional testers, requires huge capital investment over short time periods, however, because the testers quickly become obsolete. Moreover, functional tests are inefficient and cumbersome because they usually have to be manually written.
Structural tests screen for manufacturing defects and attempt to ensure the manufacturing correctness of basic devices (e.g. wiring, transistors, etc.). Structural testers perform structural tests using DFT channels. Teradyne, Inc., in Boston, Mass. offers structural testers. An advantage of structural testers is that their cost is considerably lower than the cost of functional testers. When testing integrated circuits, for example, a structural tester usually depends on the device itself to test its own input/output (I/O) specifications and report the pass/fail results to the tester through a limited number of connected pins. Timing defects for example are diagnosed through such a DFT feature called AC I/O loop-back that modulates its driver output (between a logical “one” and a logical “zero”) through a within device pattern generator, and strobes it back through its sense amplifier at the input path for within device comparison logic.
This approach is limited, however, because current AC I/O loop-back based structural tests cannot screen marginal (VIH/VIL) levels defects since there are no DFT knobs to change the amplitude of the driven signal. Additionally, an output level defect can be hidden by an input level defect since the two are exercised together.